1. Field of the Invention
The present invention relates to a method and apparatus for driving a display panel such as an active matrix type liquid crystal display panel.
2. Description of the Related Art
A first typical prior art method for driving a display is shown in FIG. 17. In an active matrix liquid crystal display panel 11 which forms a display apparatus 10, source lines O1 to ON and gate lines L1 to LM are formed in a matrix form and thin film transistors T are disposed at intersections of the source lines and the gate lines. Voltages from the source lines O1 to ON are selectively supplied to pixel electrodes P through the transistors T.
The source lines O1 to ON are connected to a source driver 12 composed of a semiconductor integrated circuit. The source driver 12 supplies one of eight types of reference voltages V0 to V7 which are supplied from a reference voltage source 13 to the source lines O1 to ON through terminals S1 to SN, in accordance with display data D0 to D2 consisting of three bits which respectively correspond to the source lines Ok (k=1 to N). A gate driver 14 composed of a semiconductor integrated circuit outputs gate signals G1 to GM to the gate lines L1 to LM. In one horizontal scanning period, the source driver 12 provides each source line Ok with a reference voltage which is based on the display data D0 to D2 which correspond to the respective pixel electrodes P each receiving each gate signal Gj (j=1 to M).
FIG. 18 is a block diagram specifically showing a partial structure of the source driver 12 of FIG. 17. The source driver 12 comprises decoder circuits FRk (k=1 to N) each corresponding to each one of the source lines O1 to ON. In response to data d0 to d2 corresponding to the display data D0 to D2, the source driver 12 selectively supplies the eight types of the reference voltages V0 to V7 from the reference voltage source 13 to the source line Ok through analog switches ASW0 to ASW7, thereby realizing 8-gradation display.
According to FIGS. 17 and 18, in the source driver 12, the reference voltages V0 to V7 corresponding to the respective gradation levels are independently supplied from the reference voltage source 13. The source driver 12 must comprise the same number of connection terminals as the reference voltages so as to receive the reference voltages V0 to V7 at the connection terminals, and further, the source driver 12 must comprise the analog switches ASW0 to ASW7 which correspond to the respective gradation levels so as to output the reference voltages.
The analog switches ASW0 to ASW7 disposed within the source driver 12 must have sufficiently low ON-resistances, so that the level of a selected one of the reference voltages V0 to V7 is accurately written in each one of the source lines O1 to ON of the display panel 11 which are connected externally to the source driver 12. Hence, in general, the area needed to dispose the analog switches ASW0 to ASW7 within a semiconductor chip must be approximately ten times as large as that in a logic circuit element which is ON/OFF-controlled for the purpose of a logic operation within the source driver 12.
Due to this, the analog switches ASW0 to ASW7 occupy a large area within the area in which the semiconductor chip set of the source driver 12 is formed. Therefore, an increase in the number of the analog switches ASW0 to ASW7 to realize an increased number of gradation levels directly results in an increase in the size of the semiconductor chip.
While a semiconductor chip set such as the source driver 12 has been improved over the recent years to reduce the chip size, there is a limit in reducing the size of a terminal itself. A reduction in the number of connection terminals is therefore desired. Further, it is desired to reduce the number of the analog switches ASW0 to ASW7 which are included in the source driver 12, for instance, to thereby reduce the chip size of the source driver 12 which is formed by a semiconductor integrated circuit and to reduce a cost.
In the first prior art, method when 16-level gradation display is to be realized using 4-bit display data, for example, connection terminals for receiving reference voltages to generate sixteen types of voltages are necessary, and further, sixteen analog switches in total each corresponding to each one of the reference voltages are necessary. Hence, in reality, it is impossible to perform mass production of the source driver 12 for conducting higher level gradation display, such as 64-level gradation display and 256-level gradation display.
As a second prior art, method Japanese Unexamined Patent Publication JP-A 4-214594 (1992) discloses an arrangement which reduces the number of connection terminals for reference voltages and the number of analog switches to thereby reduce the size of a semiconductor chip. FIG. 19 shows a schematic structure of a display apparatus disclosed in JP-A 4-214594.
Of a pair of substrates which face each other through liquid crystal, one substrate comprises pixel electrodes 16, drain lines 17, gate lines 18, and switching elements 19 which are disposed at intersections of the drain lines 17 and the gate lines 18 to supply voltages at the drain lines 17 to the pixel electrodes 16. In the other substrate, data electrodes 20 each extending in a vertical direction in FIG. 19 are formed to correspond to the respective rows.
A control pulse is supplied to the gate lines 18 so that a scanning circuit 21 defines a horizontal scanning period. During the horizontal scanning period, a reference gradation signal whose voltage varies at a constant ratio is applied to the pixel electrodes 16 through the drain lines 17. That is, a reference gradation signal circuit 23 supplies a voltage having a ramp waveform whose level increases or decreases with time within the horizontal scanning period, commonly to the drain lines 17. A data signal supply circuit 22 provides the data electrodes 20 with a data signal whose voltage level remains finalized at only during a period which corresponds to the gradation level of the data signal but becomes an high-impedance condition during other periods. In short, the data electrodes 20 receive a voltage whose level remains finalized only during a period which corresponds to the gradation level, so that the gradation level is adjusted by the length of the period during which the voltage level at the data electrodes 20 remains finalized.
The second prior art display apparatus described above has a big problem that it is necessary to dispose a large number of the data electrodes 20 which are divided into the rows in the other one of the substrates. The other one of the substrates which is disposed to face the pixel electrodes 16 of a liquid crystal display panel which is widely used in general at present includes only one common electrode which is formed all over these large number of pixel electrodes 16. Hence, the display panel itself must be re-designed to implement this prior art arrangement. Thus, it is difficult to implement this prior art arrangement.
Further, since the second prior art arrangement requires that the gradation levels are held on the data electrodes 20 side, it is impossible to utilize an auxiliary capacity for holding data which is conventionally often formed in the one substrate of the display panel.
Meanwhile, Japanese Unexamined Patent Publication JP-A 5-297833 (1993) discloses a third prior art method and apparatus for driving display. FIG. 20 shows a schematic structure of this prior art arrangement. A shift register 27 controls the timing of writing input data for colors R, G and B each consisting of 4 bits within a data register 28, in accordance with a clock signal CLK. Upon writing one line of input data in the data register 28, the shift register 27 transmits the written one line of input data to a data latch circuit 29 in a parallel manner so that the one line of input data is held at the data latch circuit 29.
The data held at the data latch circuit 29 are supplied to a comparison part 30 at predetermined timing. The comparison part 30 compares the data supplied from the data latch circuit 29 with a 4-bit count supplied from a 4-bit counter 31 for each one of the colors R, G and B, and supplies a result of the comparison to a selector-incorporated sample and hold circuit 32. Step wave voltages VR and VB whose levels respectively change in eight and two levels are also supplied to the selector-incorporated sample and hold circuit 32 from step wave voltage circuits 33 and 34.
Using a sample and hold capacitor which is incorporated therein, the selector-incorporated sample and hold circuit 32 performs sampling and holding on a level signal supplied from the step wave voltage circuits 33 and 34 corresponding to the result of the comparison which is yielded by the comparison part 30. Receiving a voltage VDD, an output buffer 35 outputs a signal voltage, which corresponds to a charging voltage level which is charged in the capacitor which is incorporated in the selector-incorporated sample and hold circuit 32, for each one of the colors R, G and B, so that the signal voltage is supplied to the lines for every row.
In the third prior art, apparatus the selector-incorporated sample and hold circuit 32 includes the sample and hold capacitor, and an operational amplifier which is formed in each line within the output buffer 35 causes a voltage follower to output a potential which is determined by a charge which is accumulated in the capacitor. Hence, outputs from the step wave voltage circuits 33 and 34 are supplied only to the capacitor of the selector-incorporated sample and hold circuit 32, but are not supplied directly to the lines of the display panel. Since voltages which are supplied to the lines of the display panel are voltages which are amplified by operational amplifiers which are disposed within the output buffer 35, a variation in characteristics of the operational amplifiers undesirably change the voltages which are supplied to the lines, and hence, deteriorates the quality of displaying. The characteristics of the operational amplifiers vary when there is a deviation of output voltage because of a variation in input offset voltage, when an output voltage range becomes narrow due to a limited dynamic range of the operational amplifiers.
Further, Japanese Examined Patent Publication JP-B2 7-50389 (1995) discloses a fourth prior art method and apparatus for driving a display. FIG. 21 is a block diagram showing the structure of an X-driver 120 for driving source electrodes disclosed in the prior art. FIG. 22 is a timing chart of signals which are used in the X-driver 120.
A shift register 121 controls the timing of 4-bit writing data input signals PD1 to PD4 in four half latches 129 of a latch A-circuit 122, in accordance with a start pulse XSP and a clock signal XCL. The latch A-circuit 122 includes M pairs of the four half latches 129. When the M pairs of the half latches 129 hold data, a latch clock signal LCL as that shown in FIG. 22 is supplied to half latches 130 of a latch B-circuit 123, whereby the data are held.
A 4-bit binary counter 124 is reset by the latch signal LCL and counts a gradation basic signal F16 as that shown in FIG. 22. M comparison elements 138 of a comparator 125 receive outputs QA to QD from the binary counter 124 and outputs from the half latches 130, and supplies a result of comparison as an output signal Y as that shown in FIG. 22 to an input D of a D flip-flop 126. The D flip-flop 126 receives outputs from the comparison elements 138 in synchronization to a rise of the gradation basic signal F16. The D flip-flop 126 is set by the latch signal LCL and reset by a stop signal STOP. An output from the D flip-flop 126 is increased up to such a voltage with which a level shifter 127 can drive an analog switch 128.
A video voltage VID as that shown in FIG. 22 is supplied to the analog switch 128, and the analog switch 128 is opened and closed under the control of an output from the level shifter 127. The video voltage VID linearly varies from an OFF-level voltage VOFF to an ON-level voltage VON of liquid crystal, during one horizontal scanning period TH.
As the analog switch 128 is opened and closed, the video voltage VID which varies in the manner described above is applied to pixel electrodes of a liquid crystal display panel through source signal lines, as a voltage VPIX as that shown in FIG. 22. The voltage VPIX is held from a time ta at which the gradation basic signal F16 rises after the output signal Y falls until a time tb at which the horizontal scanning period TH ends.
Since the fourth prior art apparatus requires that the video voltage VID which is supplied to source electrodes through the analog switch 128 has a linear sawtooth waveform, when the timing at which the comparison elements 138 outputs an output signal is subtly shifted, a voltage at this timing is held. This deteriorates the quality of displaying.